fRAC
  • Quick Start
    • Requirements
      • Hardware
      • Software
    • Generating bitstream
    • Setting up the NIC (Skip to the next section)
    • Building libtpa (Skip to the next section)
    • Setup Hugepages (Skip to the next section)
    • Connect the Hardware (Skip to the next section)
    • Program the FPGA
    • Configure the Host Network (Skip to the next section)
    • Check the TCP Connection
    • Reconfigure with an Accelerator
    • Performance Measurements
  • Integrating Your Own Accelerator
    • Creating files
    • Write an Accelerator
    • Try It on Hardware
  • Reproducing Results
    • Testbeds
    • Before You Start
      • Install the Python Packages (Skip to the next section)
      • Set the Network Interface
    • Latency vs Throughput (Figure 13)
    • Mixed Workload (Figure 14)
    • Reassembly (Figure 15)
    • Scalability and Tail Latency (Figures 16 and 17)
    • CPU Baseline (Figure 16)
    • Azure Trace (Figure 18)
  • Network-Driven Reconfiguration Controller
    • Motivation
    • Scope
    • Module Architecture
    • Runtime Reconfiguration Sequence
    • Decoupling
      • Implemented Versus Intended Isolation
    • HBM Operations
      • Write HBM
      • Read HBM
      • Reconfiguration Read Path
    • ICAP Interface
    • Status Management
    • Reset Behavior
    • Trust Boundary
  • Reconfiguration Network Protocol
    • Transport
    • fRAC Request Header
    • Command Format
    • Opcodes
      • WRITE_HBM
      • READ_HBM
      • RECONF_ICAP
      • QUERY_STATUS
    • Validation Order
    • Standard Status Response
    • Error Codes
    • Query Status Response
    • Example Encoding
    • Protocol Limitations
  • Build and Deployment
    • Requirements
    • Building
      • Build options
    • Loading Bitstreams
      • Full image
      • Partial bitstreams
    • ICAP Partial-Bitstream Format
    • Recovery
  • Verification and Implementation Status
    • Test Environment
    • Controller Unit Tests
    • Network Integration Tests
    • Accelerator Tests
    • Hardware Correctness Check
    • Missing Verification
    • Current Implementation Limitations
      • Reconfiguration Safety
      • Error-State Consistency
      • Status Visibility
      • Addressing and AXI
      • Concurrent Requests
      • DFX Build
      • Security
    • Intended Safety Sequence
    • Open Items
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